A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store a data bit. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline.
In a semiconductor memory device of the type described above, data may be written to or read from the memory cells of the array using a memory cycle that is divided into a precharge phase and an active phase, with the precharge phase being used to precharge the bitlines to a precharge voltage, and the active phase being used to read or write one or more memory cells of the array. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline.
As transistor dimensions continue to shrink, it is becoming increasingly difficult to prevent local mismatch between the memory cell transistors of the memory device. This can adversely impact memory device performance, such as the ability to consistently write data to the memory cells at low voltages. For example, a conventional six-transistor (6T) static random access memory (SRAM) memory cell includes two NMOS pass gate transistors and a pair of cross-coupled inverters, with the two inverters collectively comprising two PMOS pull-up transistors and two NMOS pull-down transistors. In writing data to a conventional SRAM memory cell of this type, the bitline is discharged to a logic low level and the wordline is set to a logic high level. If in a given memory cell, worst case local variations cause the threshold voltage in the NMOS pass gate transistors to increase and the threshold voltage in the PMOS pull-up transistors to decrease, then the NMOS pass gate transistor coupled to the bitline may not be able to drive the corresponding inverter input below its trip point, and the memory cell will not be written with the data. For a memory cell with worst case local variations, at lower write voltages the overdrive of the NMOS pass gate transistor decreases, since the overdrive is given by VGS-VT, where VGS denotes the gate-to-source voltage and VT denotes the threshold voltage. Similarly, at lower write voltages the overdrive of the PMOS pull-up transistor increases, since the overdrive is given by VSG-VT, where VSG denotes the source-to-gate voltage. This reduced overdrive of the NMOS pass-gate transistor may reduce its drive current below the required source current of the PMOS pull-up transistor, leading to the above-noted write failures under worst case local variations.
A conventional approach for addressing the above-described problem is to use a boost signal to provide an additional negative voltage to the bitline during the write operation. Thus, when writing to the memory cell, the bitline is discharged to the negative supply voltage VSS, and then the boost signal is enabled to further reduce the bitline voltage below VSS. This approach, which is also referred to as “negative bootstrapping,” increases the NMOS pass gate drive such that the inverter input is driven below its trip point, thereby allowing the data to be written to the memory cell under the above-noted worst case condition. An approach of this type is described in U.S. Patent Application Publication No. 2007/0109878, entitled “Memory Device with Improved Writing Capabilities.”
However, the negative bootstrapping approach has a number of significant drawbacks. For example, in this approach the bitline negative voltage must be accurately adjusted above the local threshold voltage variation of the NMOS pass gate to ensure smooth write operations, which is very difficult to do in practice, particularly given the presence of variable bitline capacitances across the wide range of rows in a typical embedded memory array. In addition, one must ensure that the additional negative voltage does not cause the bitline junction to become forward biased. This could cause the memory cells in unaccessed rows to turn on at very low voltage, potentially leading to inadvertent overwriting of the data stored in those memory cells.
A possible alternative approach is to utilize a charge pump to provide a separately-controlled VDD supply voltage to the core portion of the memory cell, where the core portion comprises the four inverter transistors in the 6T SRAM cell. During a write operation when the bitline is discharged to a logic low level, the core VDD voltage is reduced below the VDD voltage used for the pass gate transistors. This reduces the required drive current of the PMOS pull-up transistors, ensuring that the NMOS pass gate is able to drive the inverter input below its trip point, thereby allowing the data to be written to the memory cell under the above-noted worst case condition. However, this approach requires accurate charge pump circuitry as well as variable pumping capacitance over the wide range of rows of the memory array, and is therefore increasingly difficult to implement as device dimensions shrink.
Improved techniques for addressing one or more of the issues identified above are disclosed in U.S. patent application Ser. No. 12/974,441, filed Dec. 21, 2010 and entitled “Memory Device having Memory Cells with Enhanced Low Voltage Write Capability,” and U.S. patent application Ser. No. 13/031,798, filed Feb. 22, 2011 and entitled “Memory Device having Memory Cells with Write Assist Functionality,” which are commonly assigned herewith and incorporated by reference herein. For example, embodiments disclosed in the latter application include memory cells in which application of power to respective supply nodes of two cross-coupled inverters of a given memory cell is separately controlled. Such an arrangement allows accurate low voltage write performance to be achieved without the need for negative bootstrapping or charge pumps.
However, additional issues remain to be addressed in SRAM design. For example, it is becoming increasingly difficult to meet write margin, signal-to-noise margin and stability requirements in multi-port SRAM memory cells. As a result, conventional designs may increase NMOS pass gate transistor size in order to meet these requirements. Also, NMOS pull-down transistor sizes may need to be increased. Thus, increasing the number of ports in an SRAM memory cell can unduly increase power consumption and circuit area, while also adversely impacting memory device cost and performance.